1. Field of the Invention
The present invention relates to a clock control circuit for generating a plurality of clock signals in a semiconductor integrated circuit.
2. Description of the Related Background Art
FIG. 1 is a schematic diagram of a conventional data holding circuit shown in Japanese Patent Application Kokai No. 2002-215570. The data holding circuit comprises: a D-latch circuit 1 for holding and outputting a data signal D1i at a rising edge of a clock signal CK1; a D-latch circuit 2 for holding and outputting a data signal D2i at a falling edge of the clock signal CK1; a D-latch circuit 3 for holding and outputting a data signal D3i at a rising edge of a clock signal CK2; and a D-latch circuit 4 for holding and outputting a data signal D4i at a falling edge of the clock signal CK2. The signals held in these D-latch circuits 1-4 are output as data signals D1-D4, respectively, through buffers B1-B4.
On the other hand, the clock signals CK1, CK2 are generated by dividing a reference clock signal CK generated by a reference clock output circuit 5 by two at a rising timing and a falling timing, respectively, using flip-flops 6, 7.
In the data holding circuit, noise is generated by a holding operation of each of the D-latch circuits 1-4. The time of the noise generation spreads out because the D-latch circuits 1-4 perform the data signal holding operations at different times, respectively. In this way, the intensity of the noise is reduced, as compared with that which would be generated when the D-latch circuits 1-4 operate simultaneously at the same timing, thus making it possible to reduce the influence of erroneous operations due to the noise.
However, the data holding circuit has the following problems.
(1) The reference clock signal required by the data holding circuit is fast as compared with the rates of the data signals, resulting in larger power consumption.
(2) A plurality of clock supply paths are required, leading to difficulties in the layout due to a correction of the clock signals for skew.
(3) When the plurality of clock supply paths are switched, a circuit configuration therefor is complicated and large in scale.